Low carbon and environment protection become an international theme today. How to reduce chip power consumption becomes an important topic in chip development. A chip with lower power consumption is more competitive among chips of the same type.
When overall routing load of a chip is not high, power consumption of the entire chip may be reduced by reducing a frequency of the chip. However, that the overall routing load of the chip is not high does not mean that load of every chip channel is not high, and some chip channels may still have a high requirement regarding performance. Therefore, ensuring a bandwidth of each chip channel while reducing power consumption becomes a problem that needs to be solved for a network chip.
In the prior art, chip power consumption is reduced by using a manner of reducing a working frequency of a chip. However, this manner cannot perform rate limiting for a single channel of the chip, which may affect a bandwidth of a single-channel user of the chip. A further improvement is manually adjusting a rate limiting parameter of the single channel of the chip, to ensure the bandwidth of the single-channel user, thereby achieving the purpose of reducing chip power consumption without affecting a user bandwidth of each single channel.
However, this improvement in the prior art still has the following disadvantages:
1. Poor timeliness. An interval between time of adjusting a working frequency of a chip and time of adjusting a rate limiting parameter of a single channel is relatively large, which may result in poor performance of the single channel in a certain period of time and packet loss.
2. A user needs to perform some additional operations, for example, sampling load information of an input/output interface of a chip, and then adjusting a rate limiting parameter of a single channel of the chip according to the load information, which causes an additional cost for the user.